Analytical Delay Model for Distributed On-Chip RLCG Global Interconnects for Different Pole Conditions
نویسندگان
چکیده
Fast delay estimation methods, as compared to simulation techniques, are needed for incremental performance-driven layout synthesis. On-chip inductive and conductive effects are becoming predominant in deep submicron (DSM) interconnects due to increasing clock speeds; circuit complexity and interconnect lengths. Inductance causes noise in the signal waveforms, which can adversely affect the performance of the circuit and signal integrity. Elmore delay-based estimation methods, although efficient, fails to accurately estimate the delay for RLCG interconnect lines. This paper presents an analytical delay model, based on first and second moments of RLCG interconnection lines, that considers the effect of inductance and conductance for the estimation of delay in interconnection lines. Simulation results justify the efficacy of the proposed delay modelling approach.
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